Parallel Computer Architecture and Programming, Fall 2017
In-Datacenter Performance Analysis of a Tensor Processing Unit,
Norman P. Jouppi et al., International Symposium on Computer Architecture (ISCA), 2017.
Due Dec. 1st, 2pm.
Sequoia: Programming the Memory Hierarchy,
Kayvon Fatahalian et al., ACM/IEEE conference on Supercomputing, 2006.
Due Nov. 24th, 2pm.
GPUs and the Future of Parallel Computing,
Stephen W. Keckler et al., IEEE MICRO, 2011.
Due Nov. 10th, 2pm.
Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors,
Yoongu Kim et al., ISCA, 2014.
Due Oct. 27th, 2pm.
RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization,
Vivek Seshadri et al., MICRO, 2013.
Due Oct. 20th, 2pm.
Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches,
Gennady Pekhimenko et al., PACT, 2012.
Due Oct. 13th, 2pm.
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs,
Leslie Lamport, IEEE Transactions on Computers, 1979.
Due Oct. 6th, 2pm.
Foundations of the C++ Concurrency Memory Model, Hans-J. Boehm et al., PLDI 2008.
Due Oct. 6th, 2pm.
Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture,
Karthikeyan Sankaralingam et al., ISCA 2003.
Due Sept. 29nd, 2pm.
Dark Silicon and the End of Multicore Scaling, Hadi Esmaeilzadeh et al., ISCA 2011.
Due Sept. 22nd, 2pm.